1. Field of the Invention
The present invention relates to a ferroelectric memory having ferroelectric capacitors.
2. Description of the Related Art
Ferroelectric memories can retain data without a power supply, by operating their ferroelectric capacitors made of ferroelectric material, which is insulated material, as variable capacitors and utilizing remanent dielectric polarization remaining even after the voltages applied to the ferroelectric capacitors are removed. This nonvolatility is utilized to achieve a nonvolatile memory with ferroelectric memory cells (for example, FIGS. 1-4 to be described later) arranged in an array. For the ferroelectric capacitors, ferroelectric materials chiefly composed of PZT (lead zirconate titanate) or ferroelectric materials having a bismuth layer type perovskite structure such as SBT (strontium bismuth tantalate) are available.
FIG. 1 shows an overview of a ferroelectric memory which is composed of memory cells MC called 1T1C. A 1T1C memory cell consists of a single transfer transistor TR and a single ferroelectric capacitor FC for retaining a single bit of information. One end of the ferroelectric capacitor FC is connected to a bit line BLE or BLO through the transfer transistor TR. The other end of the ferroelectric capacitor FC is connected to a plate line PL. The gate of the transfer transistor TR is connected to a word line WLE or WLO.
A reference memory cell RMC connected with the bit line pair BLE, BLO has a reference capacitor FCR, which is made of a ferroelectric capacitor, and two nMOS transistors M1 and M2. The reference capacitor FCR has, for example, a capacitance intermediate between the capacitance of a ferroelectric capacitor FC containing “logic 0” and that of a ferroelectric capacitor containing “logic 1”. The nMOS transistor M1 connects the reference capacitor FCR to the bit line BLE when a reference word line RWLO is at H level. The nMOS transistor M2 connects the reference capacitor FCR to the bit line BLO when a reference word line RWLE is at H level.
FIG. 2 shows an overview of a ferroelectric memory which is composed of memory cells MC called 2T2C. A 2T2C memory cell has two transfer transistors TR1, TR2 and two ferroelectric capacitors FC1, FC2 for retaining a single bit of information. One ends of the ferroelectric capacitors FC1 and FC2 are connected to complementary bit lines BL and XBL through the transfer transistors TR1 and TR2, respectively. The other ends of the ferroelectric capacitors FC are connected to a plate line PL. The gates of the transfer transistors TR1 and TR2 are connected to a common word line WL.
Since 1T1C memory cells allow a reduction in cell size, they are adopted in ferroelectric memories for high density applications. Since 2T2C memory cells store complementary data in their two ferroelectric capacitors, they allow greater read margins. Thus, 2T2C memory cells are adopted in ferroelectric memories for high reliability applications. As above, 1T1C memory cells and 2T2C memory cells have respective segmented markets (A. Sheikholeslami and G. Gulak, “A Survey of Circuit Innovations in Ferroelectric Random-Access Memories”, Proceedings of IEEE, vol. 88, no. 5, pp. 667-689, 2000).
The inventors have also proposed a nonvolatile SRAM using new memory cells (6T2C or 6T4C) which are constituted by adding two or four ferroelectric capacitors to SRAM memory cells each consisting of six transistors (Japanese Unexamined Patent Application Publication No. 2003-203475). They have also released examples of application of these memory cells to programmable logic devices Japanese Unexamined Patent Application Publication No. 2003-198361, S. Masui et al., “Ferroelectric Memory-Based Secure Dynamically Programmable Gate Array”, IEEE Journal of Solid-State Circuits, vol. 38, no. 5, pp. 715-725, 2003).
FIG. 3 shows a 6T2C memory cell. This memory cell MC comprises: a latch LT which is composed of two CMOS inverters having their inputs and outputs connected to each other; ferroelectric capacitors FC1 and FC2 which are connected to two input/output nodes (storage nodes) S1 and S2 of the latch LT, respectively; and transfer transistors TR1 and TR2 for connecting the input/output nodes S1 and S2 to complementary bit lines BL and XBL, respectively. The sources of the pMOS transistors M1 and M3 of the CMOS inverters are connected to a power supply line VDD. The sources of the nMOS transistors M2 and M4 of the CMOS inverters are connected to the other side of power supply line VSS, connected to a ground. The gates of the transfer transistors TR1 and TR2 are connected to a common word line WL.
FIG. 4 shows a 6T4C memory cell. This memory cell MC is constituted by adding ferroelectric capacitors FC3 and FC4 to the memory cell MC of 6T2C type shown in FIG. 3. The ferroelectric capacitor FC3 is connected to the input/output node S1 at one end, and is connected to a plate line PL2 at the other end. The ferroelectric capacitor FC4 is connected to the input/output node S2 at one end, and is connected to the plate line PL2 at the other end. The other ends of the ferroelectric capacitors FC1 and FC2 are connected to a plate line PL1.
FIG. 5 shows operation modes of a nonvolatile SRAM having 6T2C memory cells or 6T4C memory cells (S. Masui et al., “Ferroelectric Memory-Based Secure Dynamically Programmable Gate Array”, IEEE Journal of Solid-State Circuits, vol. 38, no. 5, pp. 715-725, 2003, T. Miwa et al., “A 512-kbit Low-Voltage NV-SRAM with the size of conventional SRAM”, 2001 VLSI Circuit Symposium, pp. 129-132). During standby, the bit lines BL and XBL are precharged, the word lines WL are deselected (L level), and the plate lines PL (or PL1, PL2) are kept at VDD/2. In a read operation, a word line WL is selected (H level) from the standby state, and data retained in the latches LT is read to the complementary bit lines BL and XBL as read data. Since the plate lines PL, PL1, PL2 are kept at VDD/2 during standby and in a read operation, it is possible to maintain the voltage applied between the electrodes of the ferroelectric capacitors low and avoid material deterioration (imprint) of the ferroelectric capacitors.
The 6T2C type and 6T4C type nonvolatile SRAMs make the same read operation as the read operation of an SRAM having memory cells each consisting of six transistors, or in other words, read operation is done without driving the plate lines. As compared to ferroelectric memories of 1T1C type and 2T2C type in which the plate lines are driven in each read operation, data stored in 6T2C or 6T4C cell can thus be read over 10 times faster than the cases for 1T1C and 2T2C. In addition, a restriction on the possible number of reads, which has been a problem of 1T1C type cells and 2T2C type cells, is eliminated.
In a write operation, complementary write data is supplied to latches LT via the bit lines BL and XBL before the plate lines PL (or PL1, PL2) are driven from VDD/2 to H level (=VDD) and to L level (=VSS) successively, thereby programming the ferroelectric capacitors with the write data.
In a recall operation, the plate lines PL (or PL1) are driven from L level to H level while all WLs are deselected. Subsequently, the power supply VDD and VSS are supplied to the latches LT so that the logic values corresponding to the voltages occurring on the input/output nodes S1 and S2 are latched, and the data retained in the ferroelectric capacitors is read to the latches LT. In a power-off operation, the bit lines BL and XBL are precharged, the word lines WL are deselected, and the plate lines PL (or PL1, PL2) fall from VDD/2 to L level before the supply of the power supply VDD and VSS to the ferroelectric memory is stopped.
FIG. 6 shows a write operation of a conventional ferroelectric memory. In writing reverse data to a memory cell, the dielectric polarization values P of the ferroelectric capacitors connected to the nodes S1 and S2 reverse in polarity upon each write as shown by the black circles S1 and S2 on the hysteresis loops shown to the right in the diagram (reverse polarization). Here, the polarities of the black circles S1 and S2 are shown with reference to the voltage of the plate line PL.
FIG. 7 shows a hysteresis loop of the ferroelectric material to form the ferroelectric capacitors of a ferroelectric memory that operates under a power supply voltage of 3.3 V. The ferroelectric capacitors reverse in polarization when their state changes from “1” data which indicates the application of a positive voltage with reference to the plate line to “0” data which indicates the application of a negative voltage. The ferroelectric capacitors cause reverse polarization when a voltage higher than or equal to a coercive voltage Vc (or lower than or equal to −Vc) is applied between their electrodes. The coercive voltages Vc and −Vc are shown by the intersections between the hysteresis loop and the voltage axis (abscissa). In this example, ferroelectric capacitors containing “0” data cause reverse polarization when a voltage higher than or equal to +0.8 V is applied thereto. Ferroelectric capacitors containing “1” data cause reverse polarization when a voltage lower than or equal to −0.8 V is applied thereto. Due to reverse polarization, the data stored in the ferroelectric capacitors disappears. When reverse polarization is repeated, the ferroelectric material deteriorates and the residual dielectric polarization decreases/disappears. This makes it impossible to perform nonvolatile operations.
As described above, in the nonvolatile SRAMs having conventional 6T2C memory cells and 6T4C memory cells, the ferroelectric capacitors cause reverse polarization in writing reverse data to the memory cells MC. Consequently, the maximum number of rewrites to a memory cell MC is limited to 1×1013 times due to the deterioration characteristics of the ferroelectric material. Consequently, although they are capable of operation at 100 MHz or above, the nonvolatile SRAMs having 6T2C memory cells and 6T4C memory cells are unavailable to such applications that a CPU or other arithmetic circuit performs frequent write operations, and thus have only a limited market.
In order to remove the restriction on the number of rewrites, there have been proposed technologies for performing the write operations of a ferroelectric memory having 6T2C memory cells in the form of a normal write operation (volatile write operation) without reversing polarization of the ferroelectric capacitors and a store operation (nonvolatile write operation) causing reverse polarization of the ferroelectric capacitors to write data into the ferroelectric capacitors Japanese Unexamined Patent Application Publication No. Hei 9-17965, Japanese Unexamined Patent Application Publication No. 2002-229969). With no reverse polarization, dielectric polarization values move on the hysteresis loop without causing deterioration of the ferroelectric material. Thus, volatile write operations without reverse polarization have no restriction in the number of rewrites. Nevertheless, for example, in Japanese Unexamined Patent Application Publication 2002-229969, the voltage of the plate lines is kept at VDD/2 when volatile writes are performed. Since coercive voltages are typically lower than VDD/2, the conventional volatile writes have the problem that reverse polarization can occur.
In conventional ferroelectric memories capable of volatile write operations, voltages lower than or equal to the coercive voltages must be applied to the ferroelectric capacitors so as to prevent the ferroelectric capacitors from causing reverse polarization during the volatile write operations. This requires a circuit for switching the power supply lines of the latches among three types of voltages as shown in Japanese Unexamined Patent Application Publication No. Hei 9-17965. As a result, there have been the problems of complicated voltage switching control and greater circuit scale. Moreover, since a plurality of power lines must be laid, there have also been the problems of greater wiring area and smaller operating speed.